Verigy 93k Tester Manual 〈2024-2026〉

): Measures the absolute time delta between an input stimulus edge and the corresponding output transitions.

The manual instructs on setting up test flows , defining pin configurations, levels, and timing.

DC tests ensure the physical integrity of the DUT structures, checking for ESD damage, bonding failures, and leakage.

The physical enclosure containing the pin electronics cards. It is mounted on a manipulator to interface directly with wafer probers or package handlers.

A standard manufacturing manual for the 93k prioritizes a core sequence of tests to screen out defective parts as early as possible. DC Parametric Tests verigy 93k tester manual

Import or manually code the relationship between your DUT package pins and the tester channels. Group pins into functional categories (e.g., ALL_DIGITAL , POWER_PINS , JTAG_GROUP ) to streamline parameter assignments later. Step 2: Establish Levels and Power

The manual covers advanced wafer probing techniques, allowing the platform to bring the performance of final package testing into the wafer probing environment. This is critical for minimizing high-speed interface degradation during probing. 3. High-Speed and Performance Testing (HSIO)

Structural abstractions in the .pin file that segment the DUT into independent functional groups.

Run Focal Cal regularly based on shift changes, significant ambient temperature shifts ( ), or whenever changing interface hardware. Diagnostics Utilities ): Measures the absolute time delta between an

: Ensure the test head cooling fluid is at the correct temperature and pressure before re-running the calibration sequence. If you need help troubleshooting a specific issue, tell me:

Modern V93K configurations utilize Wave Scale cards to deliver high-density analog performance.

While the hardware documentation outlines what the machine can do, the software documentation outlines how to do it. The V93000 operates primarily on the SmarTest software environment. The manuals covering SmarTest are often the source of the steepest learning curve for new engineers.

The 93k platform is designed around a scalable architecture that allows for "per-pin" resources. Unlike traditional testers that share resources across multiple pins, the 93k provides dedicated timing, levels, and pattern memory for each channel. This ensures that complex System-on-Chip (SoC) devices can be tested with maximum precision. The physical enclosure containing the pin electronics cards

The V93000 Smart Scale generation is a continuation of the platform's focus on cost-efficient, high-performance testing. The documentation explains the integration of pin-scale technology to improve test efficiency. C. Direct-Probe™ Solution

Define when the tester should change or sample a signal. Test Flow Construction

It simulates the electrical environment the chip will face in the real world.

): Measures the precise time delay between an input trigger edge and the corresponding output transition. 5. Calibration, Diagnostics, and Troubleshooting